The present invention deals generally with the formation of isolation regions, and more specifically to the formation of sloped isolation regions in semiconductor devices.
In the semiconductor industry, the purpose of isolation regions is to isolate active areas that contain N-channel transistors from active areas that contain P-channel transistors. It is well known in the existing art that isolation regions prevent current flow between doped source/drain regions of a transistor and the well or substrate, having a similar doping, that is associated with an adjacent transistor. For example, the potential for leakage occurs when the P-doped region of a P-channel transistor is biased with respect to the adjacent P-well of an adjacent N-channel transistor.
One known method of forming the isolation regions is through the use of trench isolation technology. Trench isolation technology etches into the silicon substrate to form a trenched region. Within the trench region an isolation oxide is deposited. The isolation oxide provides isolation between active regions.
The overall quality of devices, which includes leakage that occurs at the junction between devices, can be affected by the shape of the trench isolation region. For example, an isolation trench having substantially vertical sidewalls is susceptible to the formation of keyhole voids during subsequent oxide filling of the trench. Such keyholes (voids) cause reliability issues and are not acceptable for formation of semiconductor devices.
The use of tapered trench isolation regions reduces the effects of keyholes during the formation of isolation trench regions. Specifically, tapered isolation trenches are formed having a larger opening at their top (nearer the substrate surface), and a smaller opening at their bottom to reduce the keyhole effects. However, tapering of the isolation region from wider at the surface to narrower at the bottom makes devices more susceptible to leakage between adjacent wells and junctions. Because of the tapering, a reduced distance between the adjacent well and the junction results in a greater susceptibility to leakage. Furthermore, when the device is scaled, the depth of the isolation trench must also be reduced to maintain the same aspect ratio of the trench, thereby further minimizing the distance between the junction and the adjacent well and further aggravating the leakage problem. Another drawback of tapered trenches is that they reduce the packing density of devices on a wafer.
Another known method for reducing the effects of keyholes is to reduce the trench depth. Processes can more readily form oxide isolation regions without the problem of keyholes by reducing the aspect ratio of the isolation trench. However, reducing the isolation trench depth also decreases the distance between the junction and the adjacent well. As mentioned previously, if more aggressive design rules are implemented, the trench depth must be scaled proportionally to maintain substantially the same aspect ratio to limit keyholes.
Therefore, a method and/or device capable of providing improved isolation between active regions would be beneficial.